Phases
Competition phases of Vision hardware
This competition invites researchers and professionals to create a comprehensive system design for a computer vision application. The aim is to develop a design that meets the application requirements, with clear justifications and a structured breakdown, enabling fresh graduates to implement and test the system. This competition emphasizes practical, real-world computer vision solutions that are feasible for implementation in hardware, software, and firmware domains.
First
Target Application
Computer vision applications are varied and include essential tasks such as object
detection, image segmentation, motion tracking, scene reconstruction, and
anomaly detection, among others. Each of these applications requires specific
neural network operations that demand high processing efficiency and low latency
to be effective in real-time. Therefore, an ASIC chip designed for computer
vision must support a diverse set of operations that enable these applications
to run smoothly and accurately.
The chip must also demonstrate its capability by performing competitively
on the MLPerf Inference Benchmark
First
The foundational operations
That need hard ware acceleration on such a chip include convolutions and depthwise separable convolutions, as they are critical for feature extraction in Convolutional Neural Networks (CNNs). This support is essential, given that convolutions are computation-intensive but crucial for detecting patterns, edges, and textures across applications like object detection and face recognition. Additionally, attention mechanisms found in Vision Transformers [1] (ViTs) are increasingly used in state-of-the-art models, as they improve performance on complex recognition and classification tasks by allowing the model to focus on important image regions. These mechanisms rely on efficient matrix multiplication and memory management, both of which should be optimized on the chip.
First
To handle common neural network architectures
The ASIC should also support batch normalization and activation functions (such as ReLU, Swish, and GELU) to enable fast, smooth training and inference cycles. Pooling layers and residual connections are also necessary, as they facilitate hierarchical feature extraction and allow for deeper networks, which are common in advanced applications. Moreover, many computer vision applications, such as real-time object detection and semantic segmentation, also require the chip to handle upsampling and downsampling operations, which allow the network to focus on different spatial resolutions. Since many computer vision applications are deployed in resource-constrained environments, the chip must also support quantization and mixed-precision arithmetic. These techniques reduce the model size and enhance power efficiency, which is particularly advantageous for edge applications like autonomous vehicles and surveillance systems. By incorporating these capabilities, the ASIC can deliver high performance, and energy efficiency, ensuring it meets the diverse needs of modern computer vision tasks across a wide range of devices and platforms.
First
Running an end-to-end workload requires
A complete software stack to map high-level models to the programming interface of the
target accelerator. Frameworks like TensorFlo and PyTorch allow easy model
expression and scalable training, enabling seamless compilation for deployment
on the target accelerator. Below is an example of an open sourced deep learning
acceleration stack called
VTA
- Figure 1: The VTA stack showing the various hardware and software components involved in processing workloads. Source
Objectives
01Application-Focused Design
Create a research-backed design for a computer vision application that addresses specified application requirements.
02Justification
Provide a well-supported explanation for how and why this design meets the requirements.
03Educational Task Breakdown
Break down the design into structured tasks that fresh graduates in software, hardware, and firmware can understand and implement.
04Testing and Validation Plan
Develop a robust testing and validation plan to guide implementation and ensure quality.
05Compelte Software Stack Specs
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Contest Submission Guidelines
The final expected deliverable for the contest is a document composed of 3 main sections which are:
Research & Design Proposal
- Research: Participants are expected to conduct in-depth research on state of the art SoC design targeting computer vision. They are allowed to choose an already existing designs that meet the requirements. In addition, they have their space for innovation and creativity to build upon the state of the art. In the latter case, a justification based on thorough analysis is further required; this effort is taken into consideration when evaluating a contest entry. Accordingly, the first section should provide a brief literature review of chip architecting efforts that have been made.
- Design Proposal: The next subsection represents a conclusion on the previous subsection. It can either select one of the previous papers as a candidate paper for the participant’s proposal or it can be an innovation of the participants where they can modify the design to yield better figure of merits for the design.
- Justification: The final subsection of the first section is the justification for slecting the candidate paper and/or the innovative modifications introduced by the participant. It has to be based on an elaborate comparison between the references used by the participant
Research & Design Proposal
- Research: Participants are expected to conduct in-depth research on state of the art SoC design targeting computer vision. They are allowed to choose an already existing designs that meet the requirements. In addition, they have their space for innovation and creativity to build upon the state of the art. In the latter case, a justification based on thorough analysis is further required; this effort is taken into consideration when evaluating a contest entry. Accordingly, the first section should provide a brief literature review of chip architecting efforts that have been made.
- Design Proposal: The next subsection represents a conclusion on the previous subsection. It can either select one of the previous papers as a candidate paper for the participant’s proposal or it can be an innovation of the participants where they can modify the design to yield better figure of merits for the design.
- Justification: The final subsection of the first section is the justification for slecting the candidate paper and/or the innovative modifications introduced by the participant. It has to be based on an elaborate comparison between the references used by the participant
Research & Design Proposal
- Research: Participants are expected to conduct in-depth research on state of the art SoC design targeting computer vision. They are allowed to choose an already existing designs that meet the requirements. In addition, they have their space for innovation and creativity to build upon the state of the art. In the latter case, a justification based on thorough analysis is further required; this effort is taken into consideration when evaluating a contest entry. Accordingly, the first section should provide a brief literature review of chip architecting efforts that have been made.
- Design Proposal: The next subsection represents a conclusion on the previous subsection. It can either select one of the previous papers as a candidate paper for the participant’s proposal or it can be an innovation of the participants where they can modify the design to yield better figure of merits for the design.
- Justification: The final subsection of the first section is the justification for slecting the candidate paper and/or the innovative modifications introduced by the participant. It has to be based on an elaborate comparison between the references used by the participant
Research & Design Proposal
- Research: Participants are expected to conduct in-depth research on state of the art SoC design targeting computer vision. They are allowed to choose an already existing designs that meet the requirements. In addition, they have their space for innovation and creativity to build upon the state of the art. In the latter case, a justification based on thorough analysis is further required; this effort is taken into consideration when evaluating a contest entry. Accordingly, the first section should provide a brief literature review of chip architecting efforts that have been made.
- Design Proposal: The next subsection represents a conclusion on the previous subsection. It can either select one of the previous papers as a candidate paper for the participant’s proposal or it can be an innovation of the participants where they can modify the design to yield better figure of merits for the design.
- Justification: The final subsection of the first section is the justification for slecting the candidate paper and/or the innovative modifications introduced by the participant. It has to be based on an elaborate comparison between the references used by the participant